module top;
wire C_in, A, B, C_out, sum;
system_clock #400 clock1(C_in);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
and a1(OUT1, A, B);
and a2(OUT3, C_in, OUT2);
xor x1(OUT2, A, B);
xor x2(sum, OUT2, C_in);
or o1(C_out, OUT3, OUT1);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>400)$stop;
endmodule
module test_adder1;
reg a,b;
reg carry_in ;
wire sum;
wire carry_out;
adder1_behavorial A1(carry_out, sum, a, b, carry_in);
initial
begin
carry_in = 0; a = 0; b = 0;
# 100 if ( carry_out != 0 | sum !== 0)
$display(" 0+0+0=00 sum is WRONG!");
else
$display(" 0+0+0=00 sum is RIGHT!");
carry_in = 0; a = 0; b = 1;
# 100 if ( carry_out != 0 | sum !== 1)
$display(" 0+0+1=01 sum is WRONG!");
else
$display(" 0+0+1=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 0;
# 100 if ( carry_out != 0 | sum !== 1)
$display(" 0+1+0=01 sum is WRONG!");
else
$display(" 0+1+0=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 1;
# 100 if ( carry_out != 1 | sum !== 0)
$display(" 0+1+1=10 sum is WRONG!");
else
$display(" 0+1+1=10 sum is RIGHT!");
carry_in = 1; a = 0; b = 0;
# 100 if ( carry_out != 0 | sum !== 1)
$display(" 1+0+0=01 sum is WRONG!");
else
$display(" 1+0+0=01 sum is RIGHT!");
carry_in = 1; a = 0; b = 1;
# 100 if ( carry_out != 1 | sum !== 0)
$display(" 1+0+1=10 sum is WRONG!");
else
$display(" 1+0+1=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 0;
# 100 if ( carry_out != 1 | sum !== 0)
$display(" 1+1+0=10 sum is WRONG!");
else
$display(" 1+1+0=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 1;
# 100 if ( carry_out != 1 | sum !== 1)
$display(" 1+1+1=11 sum is WRONG!");
else
$display(" 1+1+1=11 sum is RIGHT!");
$finish;
end
endmodule
module adder1_behavorial (carry_out, sum, a, b, carry_in);
input a, b, carry_in;
output carry_out, sum;
assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule
這次上課很有趣
