上機考試內容

module top; 

wire A, B, C, D, F, N1, N2 ,N4, F1, F2, F3, F4, G1, G2, G3, G4, A1, A2, A3, A4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

nand (N1, A, A);

nand (N2, B, B);

nand (N4, D, D);

nand (F1, D, N2, N1);

nand (F2, N4, B, N1);

nand (F3, D, C, A);

nand (F4, C, N4, A);

nand (G4, F4, F4);

nand (G3, F2, F2);

nand (G2, F3, F3);

nand (G1, F1, F1);

nand (A1, G1, G1);

nand (A2, G2, G2);

nand (A3, G3, G3);

nand (A4, G4, G4);

nand (F, A1, A2, A3, A4);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule

第10次上課 上機考練習 12/2

module top; 

wire A, B, C, D, F

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

or o1(F, F4, F3, F2, F1);

not n1(A1,A);

not n2(B1,B);

not n3(C1,C);

not n4(D1,D);

and a1(F4, A, C1, D1);

and a2(F2, A1, B1, D);

and a3(F3, B, C1, D1);

and a4(F1, C, D);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule 

and or not

module top; 

wire A, B, C, D, F , N1, N2, N3, N4, F1, F2, F3, F4, G1, G2, G3, G4, A1, A2, A3, A4

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

nand na1(F4, A, N3, N4);

nand na2(F2, N1, N2, D);

nand na3(F3, B, N3, N4);

nand na4(F1, C, D);

nand na5(G1, F4, F4);

nand na6(G2, F2, F2);

nand na7(G3, F3, F3);

nand na8(G4, F1, F1);

nand na9(N1, A, A);

nand na10(N2, B, B);

nand na11(N3, C, C);

nand na12(N4, D, D);

nand na13(A1, G1, G1);

nand na14(A2, G2, G2);

nand na15(A3, G3, G3);

nand na16(A4, G4, G4);

nand na17(F, A1, A2, A3, A4);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule

全NAND

module top; 

wire A, B, C, D, F;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

nor (A1, A, A);

nor (B1, B, B);

nor (C1, C, C);

nor (D1, D, D);

nor (A2, A, A);

nor (C2, C1, C1);

nor (D2, D1, D1);

nor (F4, A2, C2, D2);

nor (A3, A1, A1);

nor (B2, B1, B1);

nor (D3, D, D);

nor (F2, A3, B2, D3);

nor (B3, B, B);

nor (C3, C1, C1);

nor (D4, D1, D1);

nor (F3, B3, C3, D4);

nor (C4, C, C);

nor (D5, D, D);

nor (F1, C4, D5);

nor (F5, F1, F2, F3, F4);

nor (F, F5, F5);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule 

全NOR