module top;
integer ib,ia,is;
reg b,a,s;
wire out;
mux_behavioral mux1(out,a,b,s);
initial
begin
for (is=0; is<=1; is = is+1)
begin
s = is;
for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib+1)
begin
b = ib;
#10 $display("s=%d a=%d b=%d out=%d",a,b,s,out);
end
end
end
end
endmodule
module mux_behavioral(OUT, A, B, SEL);
output OUT;
input A,B, SEL;
wire A,B, SEL;
reg OUT;
always @(A or B or SEL)
OUT = (A & SEL)|(B & ~SEL );
endmodule
module top;
integer id,ic,ib,ia,is;
reg d,c,b,a,s;
wire out1,out2;
mux_behavioral mux1(out1,a,b,s);
mux_behavioral mux1(out2,c,d,s);
initial
begin
for (is=0; is<=1; is = is+1)
begin
s = is;
for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib+1)
begin
b = ib;
for (ic=0; ic<=1; ic = ic+1)
begin
c = ic;
for (id=0; id<=1; id = id+1)
begin
d = id;
#10 $display("s=%d a=%d b=%d c=%d d=%d out1=%d out2=%d",a,b,c,d,s,out1,out2);
end
end
end
end
end
end
endmodule
module mux_behavioral(OUT, A, B, SEL);
output OUT;
input A,B, SEL;
wire A,B, SEL;
reg OUT;
always @(A or B or SEL)
OUT = (A & SEL)|(B & ~SEL );
endmodule
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