上機考試內容

module top; 

wire A, B, C, D, F, N1, N2 ,N4, F1, F2, F3, F4, G1, G2, G3, G4, A1, A2, A3, A4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

nand (N1, A, A);

nand (N2, B, B);

nand (N4, D, D);

nand (F1, D, N2, N1);

nand (F2, N4, B, N1);

nand (F3, D, C, A);

nand (F4, C, N4, A);

nand (G4, F4, F4);

nand (G3, F2, F2);

nand (G2, F3, F3);

nand (G1, F1, F1);

nand (A1, G1, G1);

nand (A2, G2, G2);

nand (A3, G3, G3);

nand (A4, G4, G4);

nand (F, A1, A2, A3, A4);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule

第10次上課 上機考練習 12/2

module top; 

wire A, B, C, D, F

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

or o1(F, F4, F3, F2, F1);

not n1(A1,A);

not n2(B1,B);

not n3(C1,C);

not n4(D1,D);

and a1(F4, A, C1, D1);

and a2(F2, A1, B1, D);

and a3(F3, B, C1, D1);

and a4(F1, C, D);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule 

and or not

module top; 

wire A, B, C, D, F , N1, N2, N3, N4, F1, F2, F3, F4, G1, G2, G3, G4, A1, A2, A3, A4

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

nand na1(F4, A, N3, N4);

nand na2(F2, N1, N2, D);

nand na3(F3, B, N3, N4);

nand na4(F1, C, D);

nand na5(G1, F4, F4);

nand na6(G2, F2, F2);

nand na7(G3, F3, F3);

nand na8(G4, F1, F1);

nand na9(N1, A, A);

nand na10(N2, B, B);

nand na11(N3, C, C);

nand na12(N4, D, D);

nand na13(A1, G1, G1);

nand na14(A2, G2, G2);

nand na15(A3, G3, G3);

nand na16(A4, G4, G4);

nand na17(F, A1, A2, A3, A4);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule

全NAND

module top; 

wire A, B, C, D, F;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

nor (A1, A, A);

nor (B1, B, B);

nor (C1, C, C);

nor (D1, D, D);

nor (A2, A, A);

nor (C2, C1, C1);

nor (D2, D1, D1);

nor (F4, A2, C2, D2);

nor (A3, A1, A1);

nor (B2, B1, B1);

nor (D3, D, D);

nor (F2, A3, B2, D3);

nor (B3, B, B);

nor (C3, C1, C1);

nor (D4, D1, D1);

nor (F3, B3, C3, D4);

nor (C4, C, C);

nor (D5, D, D);

nor (F1, C4, D5);

nor (F5, F1, F2, F3, F4);

nor (F, F5, F5);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule 

全NOR

第9次上課 3位元加法器 11/25

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

感謝朱巖提供

第八次上課 一位元全加法器

module top; 

wire C_in, A, B, C_out, sum;

system_clock #400 clock1(C_in);

system_clock #200 clock2(A); 

system_clock #100 clock3(B);

and a1(OUT1, A, B);

and a2(OUT3, C_in, OUT2);

xor x1(OUT2, A, B);

xor x2(sum, OUT2, C_in);

or o1(C_out, OUT3, OUT1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>400)$stop; 

endmodule 

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
                $display(" 0+1+0=01 sum is WRONG!");
              else
                $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
                $display(" 0+1+1=10 sum is WRONG!");
              else
                $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
                $display(" 1+0+0=01 sum is WRONG!");
              else
                $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
                $display(" 1+0+1=10 sum is WRONG!");
              else
                $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out != 1 | sum !== 0)
                $display(" 1+1+0=10 sum is WRONG!");
              else
                $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule


這次上課很有趣

第七次上課用for迴圈替代 11/4

module top;

  integer ib,ia,is;

  reg  b,a,s;

  wire out;

  mux_behavioral mux1(out,a,b,s);

  initial

    begin

      for (is=0; is<=1; is = is+1)

       begin

         s = is;

          for (ia=0; ia<=1; ia = ia+1)

           begin

            a = ia;

             for (ib=0; ib<=1; ib = ib+1)

              begin

               b = ib;

                 #10 $display("s=%d a=%d b=%d  out=%d",a,b,s,out);

               end

            end

        end

    end

endmodule

module mux_behavioral(OUT, A, B, SEL);

 output OUT;

 input A,B, SEL;

 wire  A,B, SEL;

 reg    OUT;

  always @(A or B or SEL)

   OUT = (A & SEL)|(B & ~SEL );

endmodule

module top;

  integer id,ic,ib,ia,is;

  reg  d,c,b,a,s;

  wire out1,out2;

  mux_behavioral mux1(out1,a,b,s);

  mux_behavioral mux1(out2,c,d,s);

  initial

    begin

      for (is=0; is<=1; is = is+1)

       begin

         s = is;

          for (ia=0; ia<=1; ia = ia+1)

           begin

            a = ia;

             for (ib=0; ib<=1; ib = ib+1)

              begin

               b = ib;

                for (ic=0; ic<=1; ic = ic+1)

                 begin

                  c = ic;

                   for (id=0; id<=1; id = id+1)

                    begin

                     d = id;             

                      #10 $display("s=%d a=%d b=%d c=%d d=%d out1=%d out2=%d",a,b,c,d,s,out1,out2);

                     end

                  end

               end

            end

        end

    end

endmodule

module mux_behavioral(OUT, A, B, SEL);

 output OUT;

 input A,B, SEL;

 wire  A,B, SEL;

 reg    OUT;

  always @(A or B or SEL)

   OUT = (A & SEL)|(B & ~SEL );

endmodule

第6次上課 4位元 2+2多工器

會做3位元後4位元一下子就出來了

第6次上課 3位元多工器 2+1

終於做出來3位元多工器 2位元+1位元了