上機考試內容

module top; 

wire A, B, C, D, F, N1, N2 ,N4, F1, F2, F3, F4, G1, G2, G3, G4, A1, A2, A3, A4;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C); 

system_clock #100 clock4(D);

nand (N1, A, A);

nand (N2, B, B);

nand (N4, D, D);

nand (F1, D, N2, N1);

nand (F2, N4, B, N1);

nand (F3, D, C, A);

nand (F4, C, N4, A);

nand (G4, F4, F4);

nand (G3, F2, F2);

nand (G2, F3, F3);

nand (G1, F1, F1);

nand (A1, G1, G1);

nand (A2, G2, G2);

nand (A3, G3, G3);

nand (A4, G4, G4);

nand (F, A1, A2, A3, A4);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>800)$stop; 

endmodule